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1/51 ste2002 september 2002 n 104 x 128 bits display data ram n programmable mux rate n programmable frame rate n x,y programmable carriage return n dual partial display mode n row by row scrolling n automatic data ram blanking procedure n selectable input interface: ? i 2 c bus fast and hs-mode (read and write) ? parallel interface (read and write) ? serial interface (read and write) n fully integrated oscillator requires no external components n cmos compatible inputs n fully integrated configurable lcd bias voltage generator with: ? selectable multiplication factor (up to 6 x ) ? effective sensing for high precision output ? eight selectable temperature compensation coefficients n designed for chip-on-glass (cog) applications n low power consumption, suitable for battery operated systems n logic supply voltage range from 1.7 to 3.6v n high voltage generator supply voltage range from 1.75 to 4.2v n display supply voltage range from 4.5 to 11v n backward compatibility with ste2001 description the ste2002 is a low power cmos lcd controller driver. designed to drive a 81 rows by 128 columns graphic display, provides all necessary functions in a single chip, including on-chip lcd supply and bias voltages generators, resulting in a minimum of exter- nals components and in a very low power consump- tion. the ste2002 features three standard interfaces (serial, parallel & i 2 c) for ease of interfacing with the host m controller. type ordering number bumped wafers ste2002die1 bumped dice on waffle pack STE2002DIE2 81 x 128 single chip lcd controller / driver figure 1. block diagram column drivers row drivers data latches 104 x 128 ram display control logic scroll logic data register i 2 cbus instruction register osc co to c127 r0 to r80 osc_in vlcdin vlcdsense res vdd1,2 clock timing generator bias voltage generator high voltage generator reset test shift register vlcdout v ss sel1,2 sao test_1_14 sda_in sda_out scl parallel serial sce sdin sclk sd/c bsy_flg sa1 ext sout icon_mode vssaux icon osc_out db0 to db7 e pd/c r/w
ste2002 2/51 pin description n pad type function r0 to r80 129-169 282-322 o lcd row driver output icon 323 o icon row driver c0 to c127 1-128 o lcd column driver output v ss 236-255 gnd ground pads. v dd1 188-199 supply ic positive power supply v dd2 200-211 supply internal generator supply voltages. v lcdin 261-270 supply lcd supply voltages for the column and row output drivers. v lcdout 273-282 supply voltage multiplier output v lcdsense 271-272 supply voltage multiplier regulation input. v lcdout sensing for output voltage fine tuning v ssaux 180, 231, 218 o ground reference for selection pins configuration sel1,2 184,185 i interface mode selection ext 183 i extended instruction set selection icon_mo de 186 i icon row management sda_in 234 i i 2 c bus data in sda_out 232 o i 2 c bus data out scl 235 i i 2 c bus clock sa0 182 i i 2 c slave address bit 0 sa1 181 i i 2 c slave address bit 1 oscin 187 i external oscillator input oscout 260 o internal/external oscillator out res 230 i reset input. active low. db0 to db7 220-227 i/o parallel interface 8 bit data bus r/w 219 i parallel interface read & write control line e 229 i parallel interface data latch signal. pd/c 228 i parallel interface data/command selector sdin 214 i serial interface data input ext pad config instruction set selected vss or vssaux basic vdd1 extended icon mode pad config icon mode status vss or vssaux disabled vdd1 enabled
3/51 ste2002 sclk 217 i serial interface clock sce 216 i serial interface enable. when low the incoming data are clocked in. sd/c 215 i serial interface data/command selector sout 213 o serial out bsyflg 212 o active procedure flag. notice if there is an ongoing internal operation or an active reset. active low. t1 to t14 170-179, 256-259 i/o test pads. - a 50kohm pull-down resistor is added on input pis. pin description (continued) n pad type function test num. pin configuration test_1 test_2 test_3 test_4 open test_5 test_6 test_7 test_8 test_9 test_10 vss / vssaux test_11 test_12 test_13 test_14 vss / vssaux
ste2002 4/51 figure 2. chip mechanical drawing ste2002 col 0 vdd1 vlcdin vlcdout sa1 scl sdain sdaout vdd2 sel1 sel2 vssaux vlcdsense (0,0) x y e pd/c d0 d1 d2 d3 d4 d5 d6 d7 sclk sce sd/c sdin bsy_flg test_6 ext_set sa0 res vss test_11 test_12 test_13 test_14 col 127 row 39. row 80/icon col 63 col 64 oscin vssaux row 0 icon vlcdin vlcdsense oscout r/w sdout icon_mode vdd1 vdd2 row 34 row 40 row 75 vssaux test_4 test_5 test_3 test_10 test_8 test_9 test_7 test_2 test_1 vlcdout mark_1 mark_4 mark_3 mark_2 row 35 row 76 row 79
5/51 ste2002 figure 3. improved alth & plesko driving method v ss v 5 v 4 v 3 v 2 v lcd v ss v 5 v 4 v 3 v 2 v lcd row 0 r0 (t) row 1 r1 (t) v ss v 5 v 4 v 3 v 2 v lcd v ss v 5 v 4 v 3 v 2 v lcd col 0 c0 (t) col 1 c1 (t) v 3 - v ss 0v v 3 - v ss v lcd - v ss v ss - v 5 0v v 4 - v 5 v ss - v lcd v 4 - v lcd v ss - v 5 0v v 4 - v 5 v ss - v lcd v 4 - v lcd v state1 (t) v lcd - v 2 v 3 - v ss frame n frame n + 1 0 1 2 3 4 5 6 7 8 9 64 0v v 3 - v ss v lcd - v ss v state2 (t) v lcd - v 2 ..... ....... 0 1 2 3 4 5 6 7 8 9 64 ..... ....... d v 1 (t) d v 2 (t) d v 1 (t) = c1(t) - r0(t) d v 2 (t) = c1(t) - r1(t) d00in1154
ste2002 6/51 circuit description supplies voltages and grounds v dd2 is supply voltages to the internal voltage generator (see below). if the internal voltage generator is not used, this should be connected to v dd1 pad. v dd1 supplies the rest of the ic. v dd1 supply voltage could be different form v dd2 . internal supply voltage generator the ic has a fully integrated (no external capacitors required) charge pump for the liquid crystal display supply voltage generation. the multiplying factor can be programmed to be: auto, x6, x5, x4, x3, x2, us- ing the set cp multiplication command. if auto is set, the multiplying factor is automatically selected to have the lowest current consumption in every condition. this make possible to have an input voltage that changes over time and a constant v lcd voltage. the output voltage (v lcdout ) is tightly controlled through the v lcdsense pad. for this voltage, eight different temperature coefficients (tc, rate of change with tem- perature) can be programmed using the bits tc1 and tc0 and t2,t1 & t0. this will ensure no contrast degradation over the lcd operating range. using the internal charge pump, the v lcdin and v lcdout pads must be connected together. an external supply could be connected to v lcdin to supply the lcd without using the internal generator. in such event the v ldcout and v lcdsense must be connected to gnd and the internal voltage generator must be programmed to zero (prs = [0;0], vop = 0 - reset condition). oscillator a fully integrated oscillator (requires no external components) is present to provide the clock for the dis- play system. when used the osc pad must be connected to v dd1 pad. an external oscillator could be used and fed into the osc pin. an oscillator out is provided on the oscout pad to cascade two or more drivers bias levels to properly drive the lcd, six (including vlcd and vss) different voltage (bias) levels are generated. the ratios among these levels and vlcd, should be selected according to the mux ratio (m). they are established to be (fig. 4): figure 4. bias level generator thus providing an 1/(n+4) ratio, with n calculated from: for m = 81, n = 6 and an 1/10 ratio is set. for m = 65, n =5 and an 1/9 ratio is set. v lcd n3 + n4 + ------------ - v lcd , n2 + n4 + ------------ - v lcd , 2 n4 + ------------ - v lcd , 1 n4 + ------------ - v lcd ,v ss , r v lcd v ss v lcd v lcd v lcd v lcd n + 3 n + 4 r nr r r n + 2 n + 4 2 n + 4 1 n + 4 d00in115 0 nm3 C =
7/51 ste2002 the ste2002 provides three bits (bs0, bs1, bs2) for programming the desired bias ratio as shown below: the following table bias level for m = 65 and m = 81 are provided: lcd voltage generation the lcd voltage at reference temperature (to = 27c) can be set using the vop register content according to the following formula: v lcd (t=to) = v lcd o = (ai+v op b) (i=0,1,2) with the following values: note that the three prs values produce three adjacent ranges for vlcd. if the v op register and prs bits are set to zero the internal voltage generator is switched off. the proper value for the vlcd is a function of the liquid crystal threshold voltage (vth) and of the multiplexing rate. a general expression for this is: for mux rate m = 65 the ideal v lcd is: v lcd(to) = 6.85 v th than: bs2 bs1 bs0 n 0007 0016 0105 0114 1003 1012 1101 1110 symbol m = 65 (1/9) m = 81 (1/10) v1 v lcd v lcd v2 8/9*v lcd 9/10*v lcd v3 7/9*v lcd 8/10*v lcd v4 2/9*v v lcd 2/10*v lcd v5 1/9 *v lcd 1/10*v lcd v6 v ss v ss symbol value unit note ao 2.95 v prs = [0;0] a1 6.83 v prs = [0;1] a2 10.71 v prs = [1;0] b 0.0303 v to 27 c v lcd 1m + 21 1 m -------- - C ?? ?? ----------------------------------- - v th = v op 6.85 v th a i C () 0.03 ---------------------------------------- - =
ste2002 8/51 temperature coefficient as the viscosity, and therefore the contrast, of the lcd are subject to change with temperature, there's the need to vary the lcd voltage with temperature. the ste2002 provides the possibility to change the vlcd in a linear fashion against temperature with eight different temperature coefficient selectable through the t2, t1 and t0 bits. only four of them are available with basic instruction set (tc1 & tc0 bits). figure 5. finally, the v lcd voltage at a given (t) temperature can be calculated as: v lcd (t) = v lcd o [1 + (t-to) tc] name tc1 tc0 value unit tc0 0 0 -0.0 10 -3 1/ c tc2 0 1 -0.7 10 -3 1/c tc3 1 0 -1.05 10 -3 1/c tc6 1 1 -2.1 10 -3 1/c name tc2 tc1 tc0 value unit tc0 0 0 0 -0.0 10 -3 1/ c tc1 0 1 1 -0.35 10 -3 1/c tc2 1 0 0 -0.7 10 -3 1/c tc3 1 1 1 -1.05 10 -3 1/c tc4 1 1 1 -1.4 10 -3 1/c tc5 1 1 1 -1.75 10 -3 1/c tc6 1 1 1 -2.1 10 -3 1/c tc7 1 1 1 -2.3 10 -3 1/c 00h 01h 02h 03h 04h 05h . 7fh 00h 01h 02h 7ch 7dh 7eh 03h 04h 7dh 7eh 7fh 05h . 7ch a 1 a 0 b a 0 + b prs = [0;0] prs = [0;1] v o v lcd 00h 01h 02h 03h 04h 7dh 7eh 7fh 05h 7ch prs = [1;0] . a 2
9/51 ste2002 display data ram the ste2002, provides an 104x128 bits static ram to store display data. this is organized into 13 (bank0 to bank12) banks with 128 bytes. one of these banks (128 bits wide) can be used for icons. ram access is accomplished in either one of the bus interfaces provided (see below). allowed addresses are x0 to x127 (horizontal) and y0 to y12 (vertical). when writing to ram, four addressing mode are provided: ? normal horizontal (mx=0 and v=0), having the column with address x= 0 located on the left of the mem- ory map. the x pointer is increased after each byte written. after the last column address (x=x-car- riage), y address pointer is set to jump to the following bank and x restarts from x=0. (fig. 6) ? normal vertical (mx=0 and v=1), having the column with address x= 0 located on the left of the memory map. the y pointer is increased after each byte written. after the last y bank address (y=y-carriage), x address pointer is set to jump to next column and y restarts from y=0 (fig. 7). ? mirrored horizontal (mx=1 and v=0), having the column with address x= 0 located on the right of the memory map. the x pointer is increased after each byte written. after the last column address (x=x- carriage), y address pointer is set to jump to the next bank and x restarts from x=0 (fig. 8). ? mirrored vertical (mx=1 and v=1), having the column with address x= 0 located on the right of the mem- ory map. the y pointer is increased after each byte written. after the last y bank address (y=y-car- riage), the x pointer is set to jump to next column and y restarts from y=0 (fig. 9). after the last allowed address (x;y)=(x-carriage; y-carriage), the address pointers always jump to the cell with address (x;y) = (0;0) (fi. 10, 11, 12 & 13). data bytes in the memory could have the msb either on top (d0 = 0, fig.14) or on the bottom (d0=1, fig. 15). the ste2002 provides also means to alter the normal output addressing. a mirroring of the display along the x axis is enabled setting to a logic one my bit.this function doesn't affect the content of the memory ram. it is only related to the visualization process. when icon mode=1 the icon row is not mirrored with my and is not scrolled. when icon mode=0 the icon row is like the other graphic lines and is mirrored and scrolled. four are the multiplex ratio available when the partial display mode is disabled (mux 33, mux 49, mux 65 and mux 81). only a subset of writable rows are output on row drivers. when y-carriagemux/8 lines only 33, 49, 65 or 81 lines are visualized but it is possible to select which lines of ddram are connected on the output drivers. the ddram rows to visualized can be selected in the 0-y-carriage*8 range using the scrolling function. when y-carriage>mux lines , the icon row is moved in ddram to the first row of the y-carriage re- turn bank even if it is always connected on the same output driver. when my=0 , the icon row is output on r80 in mux 81 mode, on r72 in mux 65, on r64 in mux49 and on r56 in mux 33. when my=1 , and icon mode=1 , the icon row is output on r80 in mux 81 mode, on r72 in mux 65, on r64 in mux49 and on r56 in mux 33. when my=1 , and icon mode=0 , the icon row is output on r0 whatever is the mux rate. when icon mode =1 , the memory icon row content is output on icon pad. if not used icon pad must be left floating.
ste2002 10/51 figure 6. automatic data ram writing sequence with v=0 and data ram normal format (mx=0) 1 figure 7. automatic data ram writing sequence with v=1 and data ram normal format (mx=0) 1 figure 8. automatic data ram writing sequence with v=0 and data ram mirrored format (mx=1) 1 figure 9. automatic data ram writing sequence with v=1 and data ram mirrored format (mx=1) 1 1. x carriage=127; y-carriage = 12 0123 124125126127 bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 bank 8 bank 9 bank 10 bank 11 bank 12 0123 124125126127 bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 bank 8 bank 9 bank 10 bank 11 bank 12 127 126 125 124 3 2 1 0 bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 bank 8 bank 9 bank 10 bank 11 bank 12 127 126 125 124 3 2 1 0 bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 bank 8 bank 9 bank 10 bank 11 bank 12
11/51 ste2002 figure 10. automatic data ram writing sequence with x-y carriage return (v=0; mx=0) figure 11. automatic data ram writing sequence with x-y carriage return (v=1; mx=0) figure 12. automatic data ram writing sequence with x-y carriage return (v=0; mx=1) figure 13. automatic data ram writing sequence with x-y carriage return (v=1; mx=1) bank 0 bank 1 bank 2 y carr bank 11 bank 12 0123 124 125 126 127 x carr bank 0 bank 1 bank 2 y carr bank 11 bank 12 0123 124 125 126 127 x carr bank 0 bank 1 bank 2 y carr bank 11 bank 12 0 1 2 3 124 125 126 127 x carr bank 0 bank 1 bank 2 y carr bank 11 bank 12 0 1 2 3 124 125 126 127 x carr
ste2002 12/51 figure 14. data ram byte organization with d0 = 0 figure 15. data ram byte organization with d0 = 1 figure 16. memory rows vs. row drivers mapping with my=0, mux81, icon mode=0,1 figure 17. memory rows vs. row drivers mapping with my=0, mux 81, scroll pointer = +3, icon mode=1 0 msb lsb 1 2 3 124 125 126 127 bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 bank 8 bank 9 bank 10 bank 11 bank 12 0 lsb msb 1 2 3 124 125 126 127 bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 bank 8 bank 9 bank 10 bank 11 bank 12 row 0 row 1 row 2 row 3 r 3 r 2 r 1 r 0 r 80 row 80 0 physical memory row 1 2 3 124 125 126 127 icon row r 79 y-carriage row 79 r 3 r 2 r 1 r 0 r 80 r 79 icon row driver row driver icon mode=1 icon mode=0 row 0 row 1 row 2 row 3 r 0 r 78 r 77 row 79 row 80 0 physical memory row row driver 1 2 3 124 125 126 127 icon row r 76 icon y-carriage icon mode=1 r 1 r 80 r 79 r 2 r 3
13/51 ste2002 figure 18. memory rows vs. row drivers mapping with my=0, mux 81, scroll pointer=+3, icon mode=0 figure 19. memory rows vs. row drivers mapping with mux 65 y-carriage<=8 scroll pointer=0, icon mode=1 figure 20. memory rows vs. row drivers mapping with mux65, y-carriage>8, scroll pointer=0, icon mode=1 row 161 row 0 row 1 row 2 row 3 r 0 r 80 r 79 r 78 r 77 row 79 0 physical memory row row driver 1 2 3 124 125 126 127 icon row r 76 icon y-carriage icon mode=0 r 1 r 2 r 3 row 80 row 0 row 1 row 31 row 64 r 71 r 31 r 0 r 80 row 96 0 physical memory row row driver 1 2 3 124 125 126 127 icon row r 72 r 79 icon y-carriage row 63 r 40 r 30 row 32 n.c. n.c. row 0 row 31 row 32 row 76 row 96 0 physical memory row row driver 1 2 3 124 125 126 127 icon row row 63 y-carriage r 71 r 0 r 80 r 72 r 79 icon r 40 r 31 row 75 n.c. n.c. r 32
ste2002 14/51 figure 21. memory rows vs. row drivers mapping with mux65, y-carriage>8, scroll pointer=3, icon mode=1, figure 22. memory rows vs. row drivers mapping with my=1, mux81, icon mode 0,1 scroll pointer=0 figure 23. memory rows vs. row drivers mapping with my=1, mux81, scroll offset= +3, icon mode =0 row 0 row 1 row 2 row 33 row 34 row 76 row 96 0 physical memory row row driver 1 2 3 124 125 126 127 icon row row 66 y-carriage r 71 r 31 r 0 r 80 r 72 r 79 icon r 40 r 30 row 75 n.c. n.c. row 0 row 1 row 2 row 3 r 3 r 2 r 1 r 0 r 80 row 79 row 80 0 physical memory row row driver 1 2 3 124 125 126 127 icon row r 79 icon y-carriage row driver icon mode=1 r 80 r 79 r 78 r 2 r 1 r 0 icon icon mode=0 row 0 row 1 row 2 row 3 r 0 r 80 r 79 r 78 r 77 row 79 row 80 0 physical memory row row driver 1 2 3 124 125 126 127 icon row r 76 icon y-carriage icon mode=0 r 1
15/51 ste2002 figure 24. memory rows vs. row drivers mapping with my=1, mux81, scroll offset= +3, icon mode =1 figure 25. row drivers vs. lcd panel interconnection in mux81 mode row 0 row 1 row 2 row 3 r 0 r 78 r 77 row 79 row 80 0 physical memory row row driver 1 2 3 124 125 126 127 icon row r 76 icon y-carriage icon mode=1 scroll offset +3 r 1 r 80 r 79 r43 r42 r41 r45 r44 r40 r46 r47 r51 r50 r49 r53 r52 r48 r54 r55 r59 r58 r57 r61 r60 r56 r62 r63 r64 r 2 r 1 r 0 r 4 r 3 icon r 5 r 6 r10 r 9 r 8 r12 r11 r 7 r13 r14 r18 r17 r16 r20 r19 r15 r21 r22 r26 r25 r24 r28 r27 r23 r29 r30 r31 81x128 mux 81 mode ste2002 column drivers row drivers row drivers icon lr0012 r34 r33 r37 r36 r32 r38 r39 r68 r67 r66 r70 r69 r65 r71 r72 r73 r74 r75 r79 r80/icon r78 r77 r76 r35
ste2002 16/51 figure 26. row drivers vs. lcd panel interconnection in mux65 mode figure 27. row drivers vs. lcd panel interconnection in mux49 mode 65x128 mux 65 mode column drivers row drivers row drivers r43 r42 r41 r45 r44 r40 r46 r47 r51 r50 r49 r53 r52 r48 r54 r55 r59 r58 r57 r61 r60 r56 r62 r63 r64 r 2 r 1 r 0 r 4 r 3 icon r 5 r 6 r10 r 9 r 8 r12 r11 r 7 r13 r14 r18 r17 r16 r20 r19 r15 r21 r22 r26 r25 r24 r28 r27 r23 r29 r30 r31 ste2002 r34 r33 r37 r36 r32 r38 r39 r68 r67 r66 r70 r69 r65 r71 r72 r73 r74 r75 r79 r80/icon r78 r77 r76 r35 lr0014 icon 49x128 mux 49 mode column drivers row drivers row drivers r43 r42 r41 r45 r44 r40 r46 r47 r51 r50 r49 r53 r52 r48 r54 r55 r59 r58 r57 r61 r60 r56 r62 r63 r64 r 2 r 1 r 0 r 4 r 3 icon r 5 r 6 r10 r 9 r 8 r12 r11 r 7 r13 r14 r18 r17 r16 r20 r19 r15 r21 r22 r26 r25 r24 r28 r27 r23 r29 r30 r31 ste2002 r34 r33 r37 r36 r32 r38 r39 r68 r67 r66 r70 r69 r65 r71 r72 r73 r74 r75 r79 r80/icon r78 r77 r76 r35 lr0013 icon
17/51 ste2002 figure 28. row drivers vs. lcd panel interconnection in mux33 mode i nstruction set two different instructions formats are provided: - with d/c set to low commands are sent to the control circuitry. - with d/c set to high the data ram is addressed. two different instruction set are embedded: the ste2001-like instruction set and the extended instruction set. to select the ste2001-like instruction set the ext pad has to be connected to a logic low (connect to vss). to select the ext ended instruction the ext pad has to be connected to a logic high (connect to vdd1). the instructions have the syntax summarized in table 1 (basic-set) and table 2 (extended set) reset (res ) at power-on, all internal registers are configured with the default value. the ram content is not defined. a reset pulse on res pad (active low) re-initialize the internal registers content (see tables 3,4,5,&6). applying a reset pulse, every on-going communication with the host controller is interrupted. after the power-on, the software reset instruction can be used to re-load the reset configuration into the internal registers the default configurations is: . a memory blank instruction can be executed to clear the ram content. 33x128 mux 33mode column drivers row drivers row drivers r43 r42 r41 r45 r44 r40 r46 r47 r51 r50 r49 r53 r52 r48 r54 r55 r59 r58 r57 r61 r60 r56 r62 r63 r64 r 2 r 1 r 0 r 4 r 3 icon r 5 r 6 r10 r 9 r 8 r12 r11 r 7 r13 r14 r18 r17 r16 r20 r19 r15 r21 r22 r26 r25 r24 r28 r27 r23 r29 r30 r31 ste2002 r34 r33 r37 r36 r32 r38 r39 r68 r67 r66 r70 r69 r65 r71 r72 r73 r74 r75 r79 r80/icon r78 r77 r76 r35 lr0106 icon - horizontal addressing (v = 0) - normal instruction set (h[1:0] = 0) - normal display (mx = my = 0) - display blank (e = d = 0) - address counter x[6: 0] = 0 and y[4: 0] = 0 - temperature coefficient (tc[1: 0] = 0) - bias system (bs[2: 0] = 0) - multiplexing ratio (m[1:0]=0) - frame rate (fr[1:0]=75hz) - power down (pd = 1) - dual partial display disabled (pe=0) - v op =0
ste2002 18/51 power down (pd = 1) when at power down, all lcd outputs are kept at v ss (display off). bias generator and v lcd generator are off (v lcdout output is discharged to v ss , and then is possible to disconnect v lcdout ). the internal oscillator is in off state. an external clock can be provided. the ram contents is not cleared. memory blanking procedure this instruction allows to fill the memory with "blank" patterns, in order to delete patterns randomly gener- ated in memory when starting up the device. this instruction substitutes (128x13) single "write" instruc- tions. it is possible to program "memory blanking procedure" only under the following conditions: - pd bit = 0 the end of the procedure will be notified on the bsy_flg pad going high (while low the procedure is running). any instruction programmed with bsy_flg low will be ignored that is, no instruction can be programmed for a period equivalent to 128x13 internal write cycles (128x13x1/fclock). the start of mem- ory blanking procedure will be between one and two fclock cycles from the last active edge (e rising edge for the parallel interface, last sclk rising edge for the serial interface, last scl rising edge for the i 2 c interface). checker board procedure this instruction allows to fill the memory with "checker-board" pattern. it is mainly intended to developers, who can now simply obtain complex module test configuration by means of a single instruction. it is possible to pro- gram "checker board procedure" only under the following conditions: - pd bit = 0 the end of the procedure will be notified on the bsy_flg pad going high, while low the procedure is running. any instruction programmed with bsy_flg low will be ignored, that is, no instruction can be programmed for a period equivalent to 128x13 internal write cycles (128x13x1/fclock). the start of memory blanking procedure will be between one and two fclock cycles from the last active edge (e rising edge for the parallel interface, last sclk rising edge for the serial interface, last scl rising edge for the i 2 c interface). scrolling function the ste2002 can scroll the graphics display in units of raster-rows. the scrolling function is achieved changing the correspondence between the rows of the logical memory map and the output row drivers. the scroll function doesn't affect the data ram content. it is only related to the visualization process. the information output on the drivers is related to the row reading sequence (the 1st row read is output on r0, the 2nd on r1 and so on). scrolling means reading the matrix starting from a row that is sequentially in- creased or decreased. after every scrolling command the offset between the memory address and the memory scanning pointer is increased or decreased by one. the offset range changes in accordance with mux rate. after 80th/81th scrolling commands in mux 81 mode, or after the 64th/65th scrolling com- mands in mux 65 mode, or after 48nd/49rd scrolling command in mux 49 mode, or after 32nd/33rd scroll- ing command in mux 33 mode, the offset between the memory address and the memory scanning pointer is again zero (cyclic scrolling). a reset scrolling pointer instruction can be executed to force to zero the offset between the memory ad- dress and the memory scanning pointer the icon row is not scrolled if icon mode =1. if icon mode=0 the last row is like a general purpose row and it is scrolled as other rows. i f the dir bit is set to a logic zero the offset register is increased by one and the raster is scrolled from top down. if the dir bit is set to a logic one the offset register is decreased by one and the raster is scrolled from bottom-up.
19/51 ste2002 dual partial display if the pe bit is set to a logic one the dual partial display mode is enabled. eight partial display modes are available. the offset of the two partial display zones is row by row programma- ble. the icon row is accessed last in each partial display frame. two sets of register for the hv-generator parameters are provided ( prs[1:0], vop[6:0], bs[2:0], cp[2:0]. ). this allows switching from normal mode to partial display mode applying one instruction. the hv generator is automatically re configured using the parameters related to the enabled mode. the parameters of the two sets of registers with the same function are located in the same position of the instruction set. the registers related to the normal mode are accessible when normal mode (pe=0) is selected, the others are accessible when the partial display mode is enabled (pe=1). to setup prs[1:0], vop[6:0], bs[2:0], cp[2:0] values the instruction flow proposed in fig.46 must be followed. to setup partial display sectors start address and partial dis- play mode no particular instruction flow has to be followed. . mux rate icon mode offset range description icon row driver with my=0 mux 33 1 0-31 icon row not scrooled r56 mux 33 0 0-32 33 line graphic matrix r56 mux 49 1 0-47 icon row not scrooled r64 mux 49 0 0-48 49 line graphic matrix r64 mux 65 1 0-63 icon row not scrooled r72 mux 65 0 0-64 65 line graphic matrix r72 mux 81 1 0-79 icon row not scrooled r80 mux 81 0 0-80 81 line graphic matrix r80 pd2 pd1 pd0 section 1 section2 reset state 0 0 0 0 8 + icon row 0 0 1 8 0 + icon row 0 1 0 8 8 + icon row 0 1 1 0 16 + icon row 000 1 0 0 16 0 + icon row 1 0 1 8 16 + icon row 1 1 0 16 8 + icon row 1 1 1 16 16 + icon row
ste2002 20/51 bus interfaces to provide the widest flexibility and ease of use the ste2002 features three different methods for interfacing the host controller. to select the desired interface the sel1 and sel2 pads need to be connected to a logic low (connect to gnd) or a logic high (connect to vdd). all the i/o pins of the unused interfaces must be connected to gnd. all interfaces are working while the ste2002 is in power down . i 2 c interface the i 2 c interface is a fully complying i 2 c bus specification, selectable to work in both fast (400khz clock) and high speed mode (3.4mhz). this bus is intended for communication between different ics. it consists of two lines: one bi-directional for data signals (sda) and one for clock signals (scl). both the sda and scl lines must be connected to a positive supply voltage via an active or passive pull-up. the following protocol has been defined: - data transfer may be initiated only when the bus is not busy. - during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as control si gnals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line, from high to low, while the clock is high, define the start condition. stop data transfer: a change in the state of the data line, from low to high, while the clock signal is high, defines the stop condition. data valid: the state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between the start and the stop conditions is not limited. the information is transmitted byte- wide and each receiver acknowledges with the ninth bit. by definition, a device that gives out a message is called "transmitter", the receiving device that gets the signals is called "receiver". the device that controls the message is called "master". the devices that are controlled by the master are called "slaves" acknowledge. each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda_in line during the acknowledge clock pulse. of course, setup and hold time must be taken into account. a master receiver must signal an end- of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case, the transmitter must leave the data line high to enable the master to generate the stop sel2 sel1 interface note 00 i 2 c read and write; fast and high speed mode 0 1 serial read and write 1 0 parallel read and write 1 1 not used
21/51 ste2002 condition. connecting sda_in and sda_out together the sda line become the standard data line. having the ac- knowledge output (sdaout) separated from the serial data line is advantageous in chip-on-glass (cog) applications. in cog applications where the track resistance from the sdaout pad to the system sda line can be significant, a potential divider is generated by the bus pull-up resistor and the indium tin oxide (ito) track resistance. it is possible that during the acknowledge cycle the ste2002 will not be able to create a valid logic 0 level. by splitting the sda input from the output the device could be used in a mode that ignores the acknowledge bit. in cog applications where the acknowledge cycle is required, it is nec- essary to minimize the track resistance from the sdack pad to the system sda line to guarantee a valid low level. to be compliant with the i 2 c-bus hs-mode specification the ste2002 is able to detect the special sequence "s00001xxx". after this sequence no acknowledge pulse is generated. since no internal modification are applied to work in hs-mode, the device is able to work in hs-mode without detecting the master code. figure 29. bit transfer and start,stop conditions definition figure 30. acknowledgment on the i 2 c-bus communication protocol the ste2002 is an i 2 c slave. the access to the device is bi-directional since data write and status read are allowed. four are the device addresses available for the device. all have in common the first 5 bits (01111). the two least sig- nificant bit of the slave address are set by connecting the sa0 and sa1 inputs to a logic 0 or to a logic 1. to start the communication between the bus master and the slave lcd driver, the master must initiate a start con- dition. following this, the master sends an 8-bit byte, shown in fig. 30, on the sda bus line (most significant bit first). this consists of the 7-bit device select code, and the 1-bit read/write designator (r/w ). all slaves with the corresponding address acknowledge in parallel, all the others will ignore the i 2 c-bus transfer. writing mode. if the r/w bit is set to logic 0 the ste2002 is set to be a receiver. after the slaves acknowledge one or more command word follows to define the status of the device. a command word is composed by two bytes. the first is a control byte which defines the co and d/c values, data line stable data valid change of data allowed start condition stop condition clock data d00in1151 start clock pulse for acknowledgement data output by receiver sclk from master data output by transmitter d00in1152 1 msb lsb 289
ste2002 22/51 the second is a data byte (fig 31). the co bit is the command msb and defines if after this command w ill follow one data byte and an other command word or if w ill follow a stream of data (co = 1 comm and word, co = 0 stream of data). the d/c bit defines whether the data byte is a command or ram data (d/c = 1 ram data, d/ c = 0 command). if co =1 and d/c = 0 the incoming data byte is decoded as a command, and if co =1 and d/c =1, the following data byte will be stored in the data ram at the location specified by the data pointer. every byte of a command word must be acknowledged by all addressed units. after the last control byte, if d/c is set to a logic 1 the incoming data bytes are stored inside the ste2002 display ram starting at the address specified by the data pointer. the data pointer is automatically updated after every byte written and in the end points to the last ram location written. every byte must be acknowledged by all addressed units. reading mode. if the r/w bit is set to logic 1 the chip will output data immediately after the slave address. if the d/c bit sent during the last write access, is set to a logic 0, the byte read is the status byte. figure 31. communication protocol serial interface the ste2002 serial interface is a bidirectional link between the display driver and the application supervisor. it consists of five lines: two for data signals (sdin, sout), one for clock signals (sclk), one for the peripheral enable (sce ) and one for mode selection (sd/c ). the serial interface is active only if the sce line is set to a logic 0. when sce line is high the serial peripheral power consumption is zero. while sce pin is high the serial interface is kept in reset. the ste2002 is always a slave on the bus and receive the communication clock on the sclk pin from the mas- ter. information are exchanged byte-wide. during data transfer, the data line is sampled on the positive sclk edge. sd/c line status indicates whether the byte is a command (sd/c =0) or ram data (sd/c =1);it is read on the eighth sclk clock pulse during every byte transfer. s s 01111 0 a0a ste2002 ack write mode read mode r/w r/w slave address co ste2002 ack command word control byte msb........lsb co last n> 0 byte ste2002 ack ste2002 ack ste2002 ack a 1 dc control byte data byte a dc control byte a 0 data byte a p s s 01111 0 a1a ste2002 ack master ack p ste2002 slave address s 01111 0 a r / w control byte c o d c 000000a s 1 a s 1 a s 1 a
23/51 ste2002 if sce stays low after the last bit of a command/data byte, the serial interface expects the msb of the next byte at the next sclk positive edge. a reset pulse on res pin interrupts the transmission. no data is written into the data ram and all the internal registers are cleared. if sce is low after the positive edge of res , the serial interface is ready to receive data. throughout sout can be read only the driver i 2 c slave address. the command sequence that allows to read i 2 c slave address is reported in fig. 34 & 35. sout is in high impedance in steady state and during data write. it is possible to short circuit dout and sdin and read i2c address without any additional lines. figure 32. serial bus protocol - one byte transmission figure 33. serial bus protocol - several byte transmission figure 34. serial bus protocol - several byte transmission msb lsb d/c sce sdin sclk d00in1159 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 d/c sce sdin sclk d00in1160 db7 db6 db5 db4 db3 db2 db1 db0 don't care db7 db6 db5 d/c sce sdin sclk d00in1160 high-z db1 db0 sout high-z don't care don't care don't care don't care don't care don't care don't care command write i2c address read db7 db6 db5 db4 db3 db2
ste2002 24/51 figure 35. reading sequence parallel interface the ste2002 parallel interface is a bidirectional link between the display driver and the application supervisor. it consists of eleven lines: eight data lines (from db7 to db0) and three control lines. the control lines are: en- able (e) for data latch, pd/c for mode selection and r/w for reading or writing. the data lines and the control line values are internally latched on e rising edge (fig. 50). when the parallel interface is selected, if r/w line is set to one, d0-d7 lines are configured as output drivers (low impedence) and it is possible to read the driver i 2 c address (fig. 51) reading sequence write a "00000000" instruction source 8 pulses on sclk and read the i2c address or status byte on sout end of reading sequence sout buffer configured in high impedence lr0078 sout buffer becomes active (low impedence) 1 note: 1) these data are not read by the display diver 2) sdin and sout can be short circuited if the processor can configure serial output buffers in high impedence during data read .
25/51 ste2002 table 1. ste2001-like instruction set instruction d/c r / w description b7 b6 b5 b4 b3 b2 b1 b0 h=0 or h=1 0000000000 read i 2 c address (with serial interface only) function set 0 0 0 0 1 mx my pd v h[0] power down management; entry mode; read status byte 0 1 pd a1 a2 d e mx my do (i 2 c interface only) write data 1 0 d7 d6 d5 d4 d3 d2 d1 d0 writes data to ram h=0 memory blank 0 0 0 0 0 0 0 0 0 1 starts memory blank procedure scroll 0 0 0 0 0 0 0 0 1 dir scrolls by one row up or down v lcd range setting 000000010 prs [0] v ldc programming range selection display control 0 0 0 0 0 0 1 d 0 e select display configuration set cp factor 0 0 0 0 0 1 0 s2 s1 s0 charge pump multiplication factor set ram y 0 0 0 1 0 0 y3 y2 y1 y0 set horizontal (y) ram address set ram x 0 0 1 x6 x5 x4 x3 x2 x1 x0 set vertical (x) ram address h=1 checker board 0 0 0 0 0 0 0 0 0 1 starts checker board procedure multiplex select 0 0 0 0 0 0 0 0 1 mux selects mux factor tc select 0 0 0 0 0 0 0 1 tc1 tc0 set temperature coefficient for v ldc output address 0 0 0 0 0 0 1 do a1 a2 no function bias ratios 0 0 0 0 0 1 0 bs2 bs1 bs0 set desired bias ratios reserved 0 0 0 1 x x x x x x not to be used set v op 001 op6 op5 op4 op3 op2 op1 op0 v op register write instruction
ste2002 26/51 table 2. extended instruction set instruction d/c r/w description b7 b6 b5 b4 b3 b2 b1 b0 h independent instructions nop 0000000000 read i 2 c address (with serial interface only) function set 0 0 0 0 1 mx my pd h[1] h[0] power down management; entry mode; extended instruction set read status byte 0 1 pd 00 d e mx my do (i 2 c interface only) write data 1 0 d7 d6 d5 d4 d3 d2 d1 d0 writes data to ram h=[0;0] ram commands memory blank 0 0 0 0 0 0 0 0 0 1 starts memory blank procedure scroll 0 0 0 0 0 0 0 0 1 dir scrolls by one row up or down v lcd range setting 00000001 prs [1] prs [0] v ldc programming range selection display control 0 0 0 0 0 0 1 d 0 e select display configuration set cp factor 0 0 0 0 0 1 0 s2 s1 s0 charge pump multiplication factor set ram y 0 0 0 1 0 0 y3 y2 y1 y0 set horizontal (y) ram address set ram x 0 0 1 x6 x5 x4 x3 x2 x1 x0 set vertical (x) ram address h=[0;1] checker board 0 0 0 0 0 0 0 0 0 1 starts checker board procedure 0 0 0 0 0 0 0 0 1 v vertical addressing mode tc select 0 0 0 0 0 0 0 1 tc1 tc0 set temperature coefficient for v ldc data format 0 0 0 0 0 0 1 do 0 0 msb position bias ratios 0 0 0 0 0 1 0 bs2 bs1 bs0 set desired bias ratios 0 0 0 1xxxxxx reserved set v op 001 op6 op5 op4 op3 op2 op1 op0 v op register write instruction h=[1;0] 0 0 0 0 0 0 0 0 0 1 software reset 000000001pe partial enable 00000001fr1fr0 frame rate control 0000001 0 m[1] m[0] mux ratio partial mode 0 0 0 0 0 1 0 pd2 pd1 pd0 partial display config 0001 pd y5 pd y4 pd y 3 pd y2 pd y1 pdy 0 1 st sector start address 001 pd y6 pd y5 pd y4 pd y 3 pd y2 pd y1 pd y0 2 nd sector start address h=[1;1] 0 0 0 0 0 0 0 0 0 1 scrolling pointer reset 000000001 x not used 00000001xx not used 0000001t2t1t0 set temperature coefficient for v ldc 000001xx x x not used 000100 yc-3 yc-2 yc-1 yc-0 y-carriage return 001 xc-6 xc-5 xc-4 xc-3 xc-2 xc-1 xc-0 x carriage return
27/51 ste2002 table 3. explanations of table 2 symbols table 4. page number table 5. display mode table 6. frame rate control table 7. vlcd range selection bit 0 1 reset state dir scroll by one down scroll by one up pd device fully working device in power down 1 v horizontal addressing vertical addressing 0 mx normal x axis addressing x axis address is mirrored. 0 my image is displayed not vertically mirrored image is displayed vertically mirrored 0 do msb on top msb on bottom 0 pe partial display disabled partial display enabled 0 h[0] select page 0 select page 1 0 mux mux 65 mux 33 0 h[1] h[0] description reset state 0 0 page 0 0 1 page 1 page 0 1 0 page 2 1 1 page 3 d e description reset state 0 0 display blank 0 1 all display segments on d=0 1 0 normal mode e=0 1 1 inverse video mode fr[1] fr[0] description reset state 0 0 65hz 0 1 70hz 75hz 1 0 75hz 1 1 80hz prs[1] prs[0] description reset state 0 0 2.94 0 1 6.78 1 0 10.62 1 1 not used
ste2002 28/51 table 8. multiplexing ratio table 9. temperature coefficient table 10. table 11. charge pump multiplication factor table 12. bias ratio m[1] m[0] description reset state 00 49 01 65 01 10 81 1 1 not used t2 t1 t0 description reset state 0 0 0 vlcd temperature coefficient 0 0 0 1 vlcd temperature coefficient 1 0 1 0 vlcd temperature coefficient 2 0 1 1 vlcd temperature coefficient 3 000 1 0 0 vlcd temperature coefficient 4 1 0 1 vlcd temperature coefficient 5 1 1 0 vlcd temperature coefficient 6 1 1 1 vlcd temperature coefficient 7 tc1 tc0 description reset state 0 0 vlcd temperature coefficient 0 0 1 vlcd temperature coefficient 2 00 1 0 vlcd temperature coefficient 3 1 1 vlcd temperature coefficient 6 cp2 cp1 cp0 description reset state 000 multiplication factor x2 001 multiplication factor x3 010 multiplication factor x4 011 multiplication factor x5 000 100 multiplication factor x6 1 0 1 not used 1 1 0 not used 1 1 1 automatic bs2 bs1 bs0 description reset state 0 0 0 bias ratio equal to 7 0 0 1 bias ratio equal to 6 0 1 0 bias ratio equal to 5 0 1 1 bias ratio equal to 4 000 1 0 0 bias ratio equal to 3 1 0 1 bias ratio equal to 2 1 1 0 bias ratio equal to 1 1 1 1 bias ratio equal to 0
29/51 ste2002 table 13. y carriage return register table 14. partial display configuration y-c[3] y-c[2] y-c[1] y-c[0] description reset state 0000 0 0 0 1 y-carriage =1 0 0 1 0 y-carriage =2 0 0 1 1 y-carriage =3 1000 0 1 0 0 y-carriage =4 0 1 0 1 y-carriage =5 .... 1 0 1 0 y-carriage =10 1 0 1 1 y-carriage =11 1 1 0 0 y-carriage =12 pd2 pd1 pd0 section 1 section2 reset state 0 0 0 0 8 + icon row 0 0 1 8 0 + icon row 0 1 0 8 8 + icon row 0 1 1 0 16 + icon row 000 1 0 0 16 0 + icon row 1 0 1 8 16 + icon row 1 1 0 16 8 + icon row 1 1 1 16 16 + icon row
ste2002 30/51 figure 36. host processor interconnection with i2c interface figure 37. host processor interconnection with serial interface vdd1 sa1 scl sdain sdaout vdd2 sel1 sel2 vssaux e pd/c d0 d1 d2 d3 d4 d5 d6 d7 sclk sce sd/c sdin bsy_flg test_6 ext_set sa0 res oscin vssaux r/w sdout icon_mode vssaux test_4 test_5 test_3 test_10 test_8 test_9 test_7 test_2 test_1 vdd1 / gnd / vssaux gnd / vssaux vdd1 / gnd / vssaux vdd1 / gnd / vssaux ste2002 m p vdd1 vdd1 / gnd / vssaux gnd / vssaux vdd1 / gnd / vssaux vdd1 / gnd / vssaux ste2002 m p vdd1 sa1 scl sdain sdaout vdd2 sel1 sel2 vssaux e pd/c d0 d1 d2 d3 d4 d5 d6 d7 sclk sce sd/c sdin bsy_flg test_6 ext_set sa0 res oscin vssaux r/w sdout icon_mode vssaux test_4 test_5 test_3 test_10 test_8 test_9 test_7 test_2 test_1 vdd1 vdd1
31/51 ste2002 figure 38. host processor interconnection with parallel interface figure 39. application schematic using an external lcd voltage generator vdd1 / gnd / vssaux vdd1 / gnd / vssaux vdd1 / gnd / vssaux ste2002 m p vdd1 sa1 scl sdain sdaout vdd2 sel1 sel2 vssaux e pd/c d0 d1 d2 d3 d4 d5 d6 d7 sclk sce sd/c sdin bsy_flg test_6 ext_set sa0 res oscin vssaux r/w sdout icon_mode vssaux test_4 test_5 test_3 test_10 test_8 test_9 test_7 test_2 test_1 gnd / vssaux vdd1 vdd1 v dd vdd2 i/o vdd1 vss2 vss1 vlcdsense vlcdout vlcdin v ss v lcd 81x 128 display 40 128 100nf 1 m f 41
ste2002 32/51 figure 40. application schematic using the internal lcd voltage generator and two separate supplies figure 41. application schematic using the internal lcd voltage generator and a single supply v dd2 v dd1 vdd2 i/o vdd1 vss2 vss1 vlcdsense vlcdout vlcdin v ss 81x 128 display 40 128 41 100nf 100nf 1 m f v dd vdd2 i/o vdd1 vss2 vss1 vlcdsense vlcdout vlcdin v ss 81 x 128 display 40 128 41 100nf 1 m f
33/51 ste2002 figure 42. power-up sequence vdd1 res sce sclk sdin sd/c pd/c e lr011 6 vdd2 r/w d0 - d7 host osc out (driver) sout sda out oscin (host) scl sdain hi-z d0 - d7 driver hi-z bsy flg reset table loaded booster off power on internal reset t vdd t w(res) t logic (res)
ste2002 34/51 figure 43. power-off sequence vdd1 res sclk sdin sd/c pd/c e sce scl sdain lr011 7 vdd2 r/w d0 - d7 host osc out (driver) sout sda out oscin (host) d0 - d7 driver hi-z bsy flg t w(res) hi-z reset table loaded
35/51 ste2002 figure 44. initialization with built-in booster figure 45. dual partial display enabling instruction flow setup normal display mode configuration set driver in power down(pd=1) set driver in normal display mode (pe=0) end of normal display mode config. set prs[1:0], vop[6:0], bs[2:0], cp[2:0], fr[1:0], tc, m[1:0] for normal display operation switch "on" booster and display control logic (pd=0) enable dual partial display end of enabling dual partial display set pe=1 optional1 set 1st sector start address set 2nd sector start address
ste2002 36/51 figure 46. dual partial display mode configuration or duty change setup partial display configuration set driver in power down(pd=1) set driver in partial display mode (pe=1) end of partial display config. set prs[1:0], vop[6:0], bs[2:0], cp[2:0] for partial display operation set driver in normal mode (pe=0) set partial display configuration (pd[2:0]) set 1st sector start address set 2nd sector start address optional
37/51 ste2002 figure 47. data ram to display mapping table 15. test pin configuration test numb. pin configuration test_1 test_2 test_3 test_4 open test_5 test_6 test_7 test_8 test_9 test_10 gnd test_11 test_12 test_13 test_14 gnd glass top view display data ram icor row lcd display data ram = "0" display data ram = "1" bank 0 bank 1 bank 2 bank 3 bank 7 bank 8 d00in1155
ste2002 38/51 absolute maximum ratings symbol parameter value unit v dd1 supply voltage range - 0.5 to + 5 v v dd2 supply voltage range - 0.5 to + 7 v v lcd lcd supply voltage range - 0.5 to + 12 v i ss supply current - 50 to +50 ma v i input voltage (all input pads) -0.5 to v dd2 + 0.5 v i in dc input current - 10 to + 10 ma i out dc output current - 10 to + 10 ma p tot total power dissipation (t j = 85c) 300 mw p o power dissipation per output 30 mw t j operating junction temperature -40 to + 85 c t stg storage temperature - 65 to 150 c electrical characteristics dc operation (v dd1 = 1.7 to 3.6 v; v dd2 = 1.75 to 4.2v; v ss1,2 = 0v; v lcd = 4.5 to 11 v; t amb =-40 to 85c; unless otherwise specified) symbol parameter test condition min. typ. max. unit supply voltages v dd1 supply voltage note 9 1.7 3.6 v v dd2 supply voltage lcd voltage internally generated 1.75 4.2 v v lcdin lcd supply voltage lcd voltage supplied externally 4.5 11 v v lcdout lcd supply voltage internally generated; note 1 4.5 11 v i(v dd1 ) supply current v dd1 = 2.8v; v lcd = 7.6v; f sclk = 0;t amb = 25c; note 3. 15 20 30 m a v dd1 = 2.8v; v lcd = 7.6v; f sclk = 1mhz;t amb = 25c; note 3, 8. osc_in=gnd; parallel port 120 150 m a i(v dd2 ) voltage generator supply current with v op = 0 and prs = [0:0] with external v lcd 1 m a v dd2 = 2.8v;v lcd =7.6v; f sclk = 0; t amb = 25c; no display load; 4x charge pump; note 2,3,6, 10 35 m a i(v dd1,2 ) total supply current v dd1, v dd2 = 2.8v; v lcd = 7.6v; 4x charge pump; f sclk = 0;t amb = 25c; no display load; note 2,3,6 25 65 m a power down mode with internal or external vlcd. note 4 35 m a i(v ldcin ) external lcd supply voltage current v dd =2.8v; v lcd =7.6v;no display load; f sclk = 0; t amb = 25c; note 3. 51015 m a logic outputs v 0h high logic level output voltage ioh=-500 m a 0.8v dd1 v dd1 v v ol low logic level output voltage iol=500 m av ss 0.2v dd1 v
39/51 ste2002 notes: 1. the maximum possible v lcd voltage that can be generated is dependent on voltage, temperature and (display) load. 2. internal clock 3. when f sclk = 0 there is no interface clock. 4. power-down mode. during power-down all static currents are switched-off. 5. f external v lcd , the display load current is not transmitted to i dd 6. tolerance depends on the temperature; (typically zero at t amb = 27c), maximum tolerance values are measured at the temper- ature range limit. 7. for tc0 to tc7 8. data byte writing mode 9.v dd1 v dd2 logic inputs v il logic low voltage level v ss 0.3v dd1 v v ih logic high voltage level 0.7v dd1 v dd2 v i in input current v in = v ss1 or v dd1 -1 1 m a logic inputs/outputs v il logic low voltage level v ss 0.3v dd1 v v ih logic high voltage level 0.7v dd1 v dd1 +0.5v v column and row driver r row row output resistance v lcd = 10v; 3k 5k kohm r col column output resistance v lcd = 10v; 5k 10k kohm v col column bias voltage accuracy no load -50 +50 mv v row row bias voltage accuracy -50 +50 mv lcd supply voltage v lcd lcd supply voltage accuracy; internally generated v dd = 2.8v; v lcd = 10v; fsclk=0; t amb =25c; no display load; note 2, 3, 6 & 7; vop = 61h, prs = 2hex -1.5 1.5 % tc0 temperature coefficient -0.010 -3 1/c tc1 -0.3510 -3 1/c tc2 -0.710 -3 1/c tc3 -1.0510 -3 1/c tc4 -1.4 10 -3 1/c tc5 -1.7510 -3 1/c tc6 -2.110 -3 1/c tc7 -2.310 -3 1/c electrical characteristics (continued) dc operation (v dd1 = 1.7 to 3.6 v; v dd2 = 1.75 to 4.2v; v ss1,2 = 0v; v lcd = 4.5 to 11 v; t amb =-40 to 85c; unless otherwise specified) symbol parameter test condition min. typ. max. unit
ste2002 40/51 figure 48. reset timing diagram electrical characteristics ac operation (v dd1 = 1.7 to 3.6v; v dd2 = 1.75 to 4.2v; v ss1,2 = 0v; v lcd = 4.5 to 11v; t amb =-40 to 85c; unless otherwise specified) symbol parameter test condition min. typ. max. unit internal oscillator f osc internal oscillator frequency v dd = 2.8v; tamb = -20 to +70 c 64 72 80 khz f ext external oscillator frequency 20 100 khz f frame frame frequency fosc or fext = 72 khz; note 1 75 hz t w(res) res low pulse width 5 m s reset pulse rejection 1 m s t logic (res) internal logic reset time 5 m s t vdd v dd1 vs. v dd2 delay 0 m s vdd1 res inputs i/o (host) lr011 8 vdd2 i/o (driver) osc out (driver) oscin (host) interface output hi-z bsy flg reset table loaded tw(res) hi-z tlogic(res)
41/51 ste2002 figure 49. i 2 c-bus timings electrical characteristics ac operation (v dd1 = 1.7 to 3.6v; v dd2 = 1.75 to 4.2v; v ss1,2 = 0v; v lcd = 4.5 to 11v; t amb =-40 to 85c; unless otherwise specified) symbol parameter test condition min. typ. max. unit i 2 c bus interface (see note 4) f scl scl clock frequency fast mode dc 400 khz high speed mode; cb=100pf (max);v dd1 =2 dc 3.4 mhz high speed mode; cb=400pf (max); v dd1 =2 dc 1.7 mhz fast mode; v dd1 =1.7v 400 khz t su;sta set-up time (repeated) start condition note 2, 3, cb=100pf 160 ns t hd;sta hold time (repeated) start condition note 2, 3, cb=100pf 160 ns t low low period of the sclh clock note 2, 3, cb=100pf 160 ns t high high period of the sclh clock note 2, 3, cb=100pf 60 ns t su;dat data set-up time note 2, 3, cb=100pf 10 ns t hd;dat data hold time note 2, 3; cb=100pf 40 ns t r;cl rise time of sclh signal note 2, 3; cb=100pf 10 ns t rcl1 rise time of sclh signal after a repeated start condition and after an acknowledge bit note 2, 3, cb=100pf 10 ns t fcl fall time of sclh signal note 2, 3, cb=100pf 10 ns t rda rise time of sdah signal note 2, 3, 4, cb=100pf 10 ns t fda fall time of sdah signal note 2, 3, 4, cb=100pf 10 80 ns t rda rise time of sdah signal note 2, 3, 4, cb=400pf 20 ns t fda fall time of sdah signal note 2, 3, 4, cb=400pf 20 160 ns t su;sto set-up time for stop condition note 2, 3, cb=100pf 160 ns c b capacitive load for sdah and sclh 100 400 pf c b capacitive load for sdah + sda line and sclh + scl line 400 pf sr sclh sdah d00in1153 t fda t rda t su;sta t hd;sta t hd;dat t su;dat t low t rcl1 t rcl t high t high t low sr p t rcl1 t fcl (1) (1) = mcs current source pull-up = rp resistor pull-up
ste2002 42/51 figure 50. parallel interface write timing figure 51. parallel interface read timing electrical characteristics (continued) ac operation (v dd1 = 1.7 to 3.6v; v dd2 = 1.75 to 4.2v; v ss1,2 = 0v; v lcd = 4.5 to 11v; t amb =-40 to 85c; unless otherwise specified) symbol parameter test condition min. typ. max. unit parallel interface t cy(en) enable cycle time v dd1 = 1.7v; write; note 2, 6 150 ns t w(en) enable pulse width 60 ns t su(a) address set-up time 30 ns t h(a) address hold time 40 ns t su(d) data set-up time 30 ns t h(d) data hold time 30 ns t su(d) data set-up time in read mode 100 ns t hu(d) data hold time in read mode 100 ns pd/c t su(a) t su(d) db0-db7 e t w(en) t ho(d) t cy(en) t h(a) r/w write pd/c t su(a) t sur(d) db0-db7 e t w(en) t hor(d) t cy(en) t h(a) r/w read don't care
43/51 ste2002 figure 52. serial interface timing notes: 1. 2. all timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to v il and v ih with an input voltage swing of v ss to v dd 3. cb is the capacitive load for each bus line. 4. for bus line loads cb between 100 and 400pf the timing parameters must be linearly interpolated 5. c vlcd is the filtering capacitor on vlcdout 6. t rise and t fall (30%-70%) = 10 ns electrical characteristics (continued) ac operation (v dd1 = 1.7 to 3.6v; v dd2 = 1.75 to 4.2v; v ss1,2 = 0v; v lcd = 4.5 to 11v; t amb =-40 to 85c; unless otherwise specified) symbol parameter test condition min. typ. max. unit serial interface t cyc clock cycle sclk v dd1 = 1.7v; write; note 2, 6 150 ns t pwh1 sclk pulse width high 60 ns t pwl1 sclk pulse width low 60 ns t s2 sce setup time 30 ns t h2 sce hold time 50 ns t pwh2 sce minimum high time 50 ns t s3 sd/c setup time 30 ns t h3 sd/c hold time 40 ns t s4 sdin setup time 30 ns t h4 sdin hold time 40 ns t s5 sout access time 100 ns t h5 sout disable time vs. sclk 100 ns t h6 sout disable time vs. sce 100 ns d/c cs t s2 t s3 t s4 t h2 t pwh2 sdin sclk t h3 t h4 t pwl1 t wh1 t s2 t cyc sout t s5 t h5 t h6 lr0001 f frame f osc 960 --------- - =
ste2002 44/51 table 16. pad coordinates name pad x ( m m) y( m m) c0 1 -3275.0 -946.5 c1 2 -3225.0 -946.11 c2 3 -3175.0 -946.5 c3 4 -3125.0 -946.5 c4 5 -3075.0 -946.5 c5 6 -3025.0 -946.5 c6 7 -2975.0 -946.5 c7 8 -2925.0 -946.5 c8 9 -2875.0 -946.5 c9 10 -2825.0 -946.5 c10 11 -2775.0 -946.5 c11 12 -2725.0 -946.5 c12 13 -2675.0 -946.5 c13 14 -2625.0 -946.5 c14 15 -2575.0 -946.5 c15 16 -2525.0 -946.5 c16 17 -2475.0 -946.5 c17 18 -2425.0 -946.5 c18 19 -2375.0 -946.5 c19 20 -2325.0 -946.5 c20 21 -2275.0 -946.5 c21 22 -2225.0 -946.5 c22 23 -2175.0 -946.5 c23 24 -2125.0 -946.5 c24 25 -2075.0 -946.5 c25 26 -2025.0 -946.5 c26 27 -1975.0 -946.5 c27 28 -1925.0 -946.5 c28 29 -1875.0 -946.5 c29 30 -1825.0 -946.5 c30 31 -1775.0 -946.5 c31 32 -1725.0 -946.5 c32 33 -1675.0 -946.5 c33 34 -1625.0 -946.5 c34 35 -1575.0 -946.5 c35 36 -1525.0 -946.5 c36 37 -1475.0 -946.5 c37 38 -1425.0 -946.5 c38 39 -1375.0 -946.5 c39 40 -1325.0 -946.5 c40 41 -1275.0 -946.5 c41 42 -1225.0 -946.5 c42 43 -1175.0 -946.5 c43 44 -1125.0 -946.5 c44 45 -1075.0 -946.5 c45 46 -1025.0 -946.5 c46 47 -975.0 -946.5 c47 48 -925.0 -946.5 c48 49 -875.0 -946.5 c49 50 -825.0 -946.5 c50 51 -775.0 -946.5 c51 52 -725.0 -946.5 c52 53 -675.0 -946.5 c53 54 -625.0 -946.5 c54 55 -575.0 -946.5 c55 56 -525.0 -946.5 c56 57 -475.0 -946.5 c57 58 -425.0 -946.5 c58 59 -375.0 -946.5 c59 60 -325.0 -946.5 c60 61 -275.0 -946.5 c61 62 -225.0 -946.5 table 16. pad coordinates (continued) name pad x ( m m) y( m m)
45/51 ste2002 c62 63 -175.0 -946.5 c63 64 -125.0 -946.5 c64 65 +125.0 -946.5 c65 66 +175.0 -946.5 c66 67 +225.0 -946.5 c67 68 +275.0 -946.5 c68 69 +325.0 -946.5 c69 70 +375.0 -946.5 c70 71 +425.0 -946.5 c71 72 +475.0 -946.5 c72 73 +525.0 -946.5 c73 74 +575.0 -946.5 c74 75 +625.0 -946.5 c75 76 +675.0 -946.5 c76 77 +725.0 -946.5 c77 78 +775.0 -946.5 c78 79 +825.0 -946.5 c79 80 +875.0 -946.5 c80 81 +925.0 -946.5 c81 82 +975.0 -946.5 c82 83 +1025.0 -946.5 c83 84 +1075.0 -946.5 c84 85 +1125.0 -946.5 c85 86 +1175.0 -946.5 c86 87 +1225.0 -946.5 c87 88 +1275.0 -946.5 c88 89 +1325.0 -946.5 c89 90 +1375.0 -946.5 c90 91 +1425.0 -946.5 c91 92 +1475.0 -946.5 c92 93 +1525.0 -946.5 table 16. pad coordinates (continued) name pad x ( m m) y( m m) c93 94 +1575.0 -946.5 c94 95 +1625.0 -946.5 c95 96 +1675.0 -946.5 c96 97 +1725.0 -946.5 c97 98 +1775.0 -946.5 c98 99 +1825.0 -946.5 c99 100 +1875.0 -946.5 c100 101 +1925.0 -946.5 c101 102 +1975.0 -946.5 c102 103 +2025.0 -946.5 c103 104 +2075.0 -946.5 c104 105 +2125.0 -946.5 c105 106 +2175.0 -946.5 c106 107 +2225.0 -946.5 c107 108 +2275.0 -946.5 c108 109 +2325.0 -946.5 c109 110 +2375.0 -946.5 c110 111 +2425.0 -946.5 c111 112 +2475.0 -946.5 c112 113 +2525.0 -946.5 c113 114 +2575.0 -946.5 c114 115 +2625.0 -946.5 c115 116 +2675.0 -946.5 c116 117 +2725.0 -946.5 c117 118 +2775.0 -946.5 c118 119 +2825.0 -946.5 c119 120 +2875.0 -946.5 c120 121 +2925.0 -946.5 c121 122 +2975.0 -946.5 c122 123 +3025.0 -946.5 c123 124 +3075.0 -946.5 table 16. pad coordinates (continued) name pad x ( m m) y( m m)
ste2002 46/51 c124 125 +3125.0 -946.5 c125 126 +3175.0 -946.5 c126 127 +3225.0 -946.5 c127 128 +3275.0 -946.5 r40 129 +3571.5 -875.0 r41 130 +3571.5 -825.0 r42 131 +3571.5 -775.0 r43 132 +3571.5 -725.0 r44 133 +3571.5 -675.0 r45 134 +3571.5 -625.0 r46 135 +3571.5 -575.0 r47 136 +3571.5 -525.0 r48 137 +3571.5 -475.0 r49 138 +3571.5 -425.0 r50 139 +3571.5 -375.0 r51 140 +3571.5 -325.0 r52 141 +3571.5 -275.0 r53 142 +3571.5 -225.0 r54 143 +3571.5 -175.0 r55 144 +3571.5 -125.0 r56 145 +3571.5 -75.0 r57 146 +3571.5 -25.0 r58 147 +3571.5 +25.0 r59 148 +3571.5 +75.0 r60 149 +3571.5 +125.0 r61 150 +3571.5 +175.0 r62 151 +3571.5 +225.0 r63 152 +3571.5 +275.0 r64 153 +3571.5 +325.0 r65 154 +3571.5 +375.0 r66 155 +3571.5 +425.0 table 16. pad coordinates (continued) name pad x ( m m) y( m m) r67 156 +3571.5 +475.0 r68 157 +3571.5 +525.0 r69 158 +3571.5 +575.0 r70 159 +3571.5 +625.0 r71 160 +3571.5 +675.0 r72 161 +3571.5 +725.0 r73 162 +3571.5 +775.0 r74 163 +3571.5 +825.0 r75 164 +3571.5 +875.0 r76 165 +3275.0 +946.5 r77 166 +3225.0 +946.5 r78 167 +3175.0 +946.5 r79 168 +3125.0 +946.5 r80/icon 169 +3075.0 +946.5 test_1 170 +2825.0 +946.5 test_2 171 +2775.0 +946.5 test_3 172 +2725.0 +946.5 test_4 173 +2675.0 +946.5 test_5 174 +2625.0 +946.5 test_6 175 +2575.0 +946.5 test_7 176 +2525.0 +946.5 test_8 177 +2475.0 +946.5 test_9 178 +2425.0 +946.5 test_10 179 +2375.0 +946.5 vssaux 180 +2225.0 +946.5 sa1 181 +2175.0 +946.5 sa0 182 +2125.0 +946.5 ext 183 +2075.0 +946.5 sel2 184 +2025.0 +946.5 sel1 185 +1975.0 +946.5 icon_mode 186 +1925.0 +946.5 table 16. pad coordinates (continued) name pad x ( m m) y( m m)
47/51 ste2002 osc_in 187 +1875.0 +946.5 vdd1_1 188 +1825.0 +946.5 vdd1_2 189 +1825.0 +839.5 vdd1_3 190 +1775.0 +946.5 vdd1_4 191 +1775.0 +839.5 vdd1_5 192 +1725.0 +946.5 vdd1_6 193 +1725.0 +839.5 vdd1_7 194 +1675.0 +946.5 vdd1_8 195 +1675.0 +839.5 vdd1_9 196 +1625.0 +946.5 vdd1_10 197 +1625.0 +839.5 vdd1_11 198 +1575.0 +946.5 vdd1_12 199 +1575.0 +839.5 vdd2_1 200 +1525.0 +946.5 vdd2_2 201 +1525.0 +839.5 vdd2_3 202 +1475.0 +946.5 vdd2_4 203 +1475.0 +839.5 vdd2_5 204 +1425.0 +946.5 vdd2_6 205 +1425.0 +839.5 vdd2_7 206 +1375.0 +946.5 vdd2_8 207 +1375.0 +839.5 vdd2_9 208 +1325.0 +946.5 vdd2_10 209 +1325.0 +839.5 vdd2_11 210 +1275.0 +946.5 vdd2_12 211 +1275.0 +839.5 busy_flag 212 +1125.0 +946.5 sdout 213 +975.0 +946.5 sdin 214 +925.0 +946.5 sd/c 215 +875.0 +946.5 sce 216 +825.0 +946.5 sclk 217 +775.0 +946.5 table 16. pad coordinates (continued) name pad x ( m m) y( m m) vssaux 218 +625.0 +946.5 r/w 219 +575.0 +946.5 d7 220 +525.0 +946.5 d6 221 +475.0 +946.5 d5 222 +425.0 +946.5 d4 223 +375.0 +946.5 d3 224 +325.0 +946.5 d2 225 +275.0 +946.5 d1 226 +225.0 +946.5 d0 227 +175.0 +946.5 pd/c 228 +125.0 +946.5 e 229 +75.0 +946.5 res 230 -75.0 +946.5 vssaux 231 -225.0 +946.5 sda_out 232 -275.0 +946.5 sda_out 233 -325.0 +946.5 sda_in 234 -375.0 +946.5 scl 235 -425.0 +946.5 vss_1 236 -975.0 +946.5 vss_2 237 -975.0 +839.5 vss_3 238 -1025.0 +946.5 vss_4 239 -1025.0 +839.5 vss_5 240 -1075.0 +946.5 vss_6 241 -1075.0 +839.5 vss_7 242 -1125.0 +946.5 vss_8 243 -1125.0 +839.5 vss_9 244 -1175.0 +946.5 vss_10 245 -1175.0 +839.5 vss_11 246 -1225.0 +946.5 vss_12 247 -1225.0 +839.5 vss_13 248 -1275.0 +946.5 table 16. pad coordinates (continued) name pad x ( m m) y( m m)
ste2002 48/51 vss_14 249 -1275.0 +839.5 vss_15 250 -1325.0 +946.5 vss_16 251 -1325.0 +839.5 vss_17 252 -1375.0 +946.5 vss_18 253 -1375.0 +839.5 vss_19 254 -1425.0 +946.5 vss_20 255 -1425.0 +839.5 test_11 256 -1475.0 +946.5 test_12 257 -1525.0 +946.5 test_13 258 -1575.0 +946.5 test_14 259 -1625.0 +946.5 osc_out 260 -2175.0 +946.5 vlcdin_1 261 -2325.0 +946.5 vlcdin_2 262 -2325.0 +839.5 vlcdin_3 263 -2375.0 +946.5 vlcdin_4 264 -2375.0 +839.5 vlcdin_5 265 -2425.0 +946.5 vlcdin_6 266 -2425.0 +839.5 vlcdin_7 267 -2475.0 +946.5 vlcdin_8 268 -2475.0 +839.5 vlcdin_9 269 -2525.0 +946.5 vlcdin_10 270 -2525.0 +839.5 vlcdsense_1 271 -2575.0 +946.5 vlcdsense_2 272 -2575.0 +839.5 vlcdout_1 273 -2625.0 +946.5 vlcdout_2 274 -2625.0 +839.5 vlcdout_3 275 -2675.0 +946.5 vlcdout_4 276 -2675.0 +839.5 vlcdout_5 277 -2725.0 +946.5 vlcdout_6 278 -2725.0 +839.5 vlcdout_7 279 -2775.0 +946.5 table 16. pad coordinates (continued) name pad x ( m m) y( m m) vlcdout_8 280 -2775.0 +839.5 vlcdout_9 281 -2825.0 +946.5 vlcdout_10 282 -2825.0 +839.5 r39 283 -3075.0 +946.5 r38 284 -3125.0 +946.5 r37 285 -3175.0 +946.5 r36 286 -3225.0 +946.5 r35 287 -3275.0 +946.5 r34 288 -3571.5 +875.0 r33 289 -3571.5 +825.0 r32 290 -3571.5 +775.0 r31 291 -3571.5 +725.0 r30 292 -3571.5 +675.0 r29 293 -3571.5 +625.0 r28 294 -3571.5 +575.0 r27 295 -3571.5 +525.0 r26 296 -3571.5 +475.0 r25 297 -3571.5 +425.0 r24 298 -3571.5 +375.0 r23 299 -3571.5 +325.0 r22 300 -3571.5 +275.0 r21 301 -3571.5 +225.0 r20 302 -3571.5 +175.0 r19 303 -3571.5 +125.0 r18 304 -3571.5 +75.0 r17 305 -3571.5 +25.0 r16 306 -3571.5 -25.0 r15 307 -3571.5 -75.0 r14 308 -3571.5 -125.0 r13 309 -3571.5 -175.0 r12 310 -3571.5 -225.0 table 16. pad coordinates (continued) name pad x ( m m) y( m m)
49/51 ste2002 figure 53. alignment marks coordinates figure 54. alignment marks dimensions table 17. bumps table 18. die mechanical dimensions r11 311 -3571.5 -275.0 r10 312 -3571.5 -325.0 r9 313 -3571.5 -375.0 r8 314 -3571.5 -425.0 r7 315 -3571.5 -475.0 r6 316 -3571.5 -525.0 r5 317 -3571.5 -575.0 r4 318 -3571.5 -625.0 r3 319 -3571.5 -675.0 r2 320 -3571.5 -725.0 r1 321 -3571.5 -775.0 r0 322 -3571.5 -825.0 icon 323 -3571.5 -875.0 x y marks -3574.5 -949.5 mark1 +3574.5 -949.5 mark2 -2250 +949.5 mark3 +1200 +949.5 mark4 table 16. pad coordinates (continued) name pad x ( m m) y( m m) bump number dimensions bumps on single row size 1-187 212-235 256-260 283-323 30 m m x 98 m m x 17.5 bumps on two rows size 188-211 236-255 261-282 30 m m x 87 m m x 17.5 pad size 1-323 43 m m x 107 m m pad pitch 1-323 50 m m spacing between bumps 1-323 20 m m die size 2.07mm x 7.32mm wafers thickness 500 m m 94 m m 39 m m
ste2002 50/51 figure 55. die orientation in tray figure 56. tray information ste2002 die identification mark 1 mark 2 mark 4 mark 3 a a array size = 13 x5 (65) units
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan -malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states. http://www.st.com 51/51 ste2002

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